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p roduct s pecification integrated circuits group LH28F128BFHED-PWTLZ8 flash memory 128mbit (8mbitx16) (model number: lhf12fz8) spec. issue date: october 26, 2004 spec no: el16x218

lhf12fz8 ? handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ? when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufact ured for the following appli cation areas. when using the products covered herein for the equipment listed in paragr aph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). ? office electronics ? instrumentation and measuring equipment ? machine tools ? audiovisual equipment ? home appliance ? communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability , should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, re dundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. ? control and safety devices for airplanes, trains, automobiles, and other transportation equipment ? mainframe computers ? traffic control systems ? gas leak detectors and automatic cutoff devices ? rescue and security equipment ? other safety devices and safety equipment, etc. (3) do not use the products covered herein for the follo wing equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. ? aerospace equipment ? communications equipment for trunk lines ? control equipment for the nuclear power industry ? medical equipment related to life support, etc. (4) please direct all queries and commen ts regarding the interpretation of the above three paragraphs to a sales representative of the company. ? please direct all queries regarding the products cove red herein to a sales representative of the company. rev. 2.44
lhf12fz8 1 pa ge 48-lead tsop pinout................................................. 3 pin descriptions.......................................................... 4 simultaneous operation modes allowed with eight planes ................................. 5 memory map .............................................................. 6 identifier codes and otp address for read operation ............................................. 8 identifier codes and otp address for read operation on partition configuration........ 8 otp block address map for otp program............... 9 bus operation........................................................... 10 command definitions ............................................... 11 functions of block lock and block lock-down..... 13 block locking state transitions upon command write................................................ 13 block locking state transitions upon wp# transition................................................. 14 status register definition......................................... 15 pag e extended status register definition ......................... 16 partition configuration register definition.............. 17 partition configuration ............................................. 17 1 electrical specifications......................................... 18 1.1 absolute maximum ratings ........................... 18 1.2 operating conditions ...................................... 18 1.2.1 capacitance .............................................. 19 1.2.2 ac input/output test conditions ............ 19 1.2.3 dc characteristics ................................... 20 1.2.4 ac characteristics - read-only operations......................... 22 1.2.5 ac characteristics - write operations ................................. 25 1.2.6 reset operations ...................................... 27 1.2.7 block erase, bank erase, (page buffer) program and otp program performance.................... 28 2 related document information.............................. 29 3 package and packing specification ........................ 30 contents rev. 2.44
lhf12fz8 2 LH28F128BFHED-PWTLZ8 128mbit (8mbit 16) page mode dual work flash memory 128m density with 16bit i/o interface ? 2 bank enable (be 0 #, be 1 #) control high performance reads ? 90/35ns 8-word page mode configurative 8-plane dual work ? flexible partitioning ? read operations during block erase or (page buffer) program ? status register for each partition low power operation ? 2.7v read and write operations ? automatic power savings mode reduces i ccr in static mode enhanced code + data storage ? 5 s typical erase/program suspends otp (one time program) block ? 4-word factory-programmed area ? 4-word user-programmable area high performance program with page buffer ? 16-word page buffer ? 5 s/word (typ.) at 12v v pp operating temperature -40 c to +85 c cmos process (p-type silicon substrate) flexible blocking architecture ? sixteen 4k-word parameter blocks ? two-hundred and fifty-four 32k-word main blocks ? top and bottom parameter location enhanced data protection features ? individual block lock and block lock-down with zero-latency ? all blocks are locked at power-up or device reset. ? absolute protection with v pp v pplk ? block erase, bank erase, (page buffer) word program lockout during power transitions automated erase/program algorithms ? 3.0v low-power 11 s/word (typ.) programming ? 12v no glue logic 9 s/word (typ.) production programming and 0.5s erase (typ.) cross-compatible command support ? basic command set ? common flash interface (cfi) extended cycling capability ? minimum 100,000 block erase cycles 48-lead tsop etox tm* flash technology not designed or rated as radiation hardened the product, which is 8-plane page mode dual work (simu ltaneous read while erase/program) flash memory, is a low power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. the product can operate at v cc =2.7v-3.6v and v pp =1.65v-3.6v or 11.7v-12.3v. its low voltage operation capability greatly extends battery life for portable applications. the product provides high performance asynchronous page mode. it allows code execution directly from flash, thus eliminating time consuming wait states. furthermore, its newly configurative partitioning architecture allows flexible dual work operation. the memory array block architecture utilizes enhanced data protection features, and provides separate parameter and main blocks that provide maximum flexibility for safe nonvolatile code and data storage. fast program capability is provided through the use of high speed page buffer program. special otp (one time program) block provides an ar ea to store permanent code such as a unique number. * etox is a trademark of intel corporation. rev. 2.44
lhf12fz8 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-lead tsop standard pinout 12mm x 20mm top view a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 21 a 20 we# rst# v pp wp# a 19 a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 16 be 1 # gnd dq 15 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe# gnd be 0 # a 0 figure 1. 48-lead tsop (normal bend) pinout rev. 2.44
lhf12fz8 4 table 1. pin descriptions symbol type name and function a 0 -a 21 input address inputs: inputs for addresses. a 0 -a 21 dq 0 -dq 15 input/ output data inputs/outputs: inputs data and commands during cui (command user interface) write cycles, outputs data during memory array, status register, query code, identifier code and partition configuration register code reads. data pins float to high- impedance (high z) when the chip or outputs are deselected. data is internally latched during an erase or program cycle. be 0 #, be 1 # input bank enable: activates the device?s control logic, input buffers, decoders and sense amplifiers. be 0 #-high (v ih ) and be 1 #-high (v ih ) deselects the device and reduces power consumption to standby levels. rst# input reset: when low (v il ), rst# resets internal automation and inhibits write operations which provides data protection. rst#-high (v ih ) enables normal operation. after power-up or reset mode, the device is automatically set to read array mode. rst# must be low during power-up/down. oe# input output enable: gates the devi ce?s outputs during a read cycle. we# input write enable: controls writes to the cui and array blocks. addresses and data are latched on the rising edge of be 0 # or be 1 # or we# (whichever goes high first). wp# input write protect: when wp# is v il , locked-down blocks cannot be unlocked. erase or program operation can be executed to the blocks which are not locked and not locked- down. when wp# is v ih , lock-down is disabled. v pp input monitoring power supply voltage: v pp is not used for power supply pin. with v pp v pplk , block erase, bank erase, (page buffer) program or otp program cannot be executed and should not be attempted. applying 12v0.3v to v pp provides fast erasing or fast programming mode. in this mode, v pp is power supply pin. applying 12v0.3v to v pp during erase/program can only be done for a maximum of 1,000 cycles on each block. v pp may be connected to 12v0.3v for a total of 80 hours maximum. use of this pin at 12v beyond these limits may reduce block cycling capability or cause permanent damage. v cc supply device power supply (2.7v-3.6v): with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltage (see dc characteristics) produce spurious results and should not be attempted. gnd supply ground: do not float any ground pins. rev. 2.44
lhf12fz8 5 notes: 1. "x" denotes the operation available. 2. configurative partition dual work restrictions: status register reflects partition state, not wsm (write st ate machine) state - this allows a status register for each partition. only one partition can be erased or programmed at a time - no command queuing. commands must be written to an address within the block targeted by that command. table 2. simultaneous operation modes allowed with eight planes (1, 2) if one partition is: then the modes allowed in the other partition is: read array read id/otp read status read query word program page buffer program otp program block erase bank erase program suspend block erase suspend read array x x x x x x x x x read id/otp x x x x x x x x x read status x x x x x x x x x x x read query x x x x x x x x x word program x x x x x page buffer program xxxx x otp program x block erasexxxx bank erase x program suspend xxxx x block erase suspend xxxx x x x rev. 2.44
lhf12fz8 6 127 128 129 130 131 132 133 4k-word 3ff000h - 3fffffh 4k-word 3fe000h - 3fefffh 4k-word 3fd000h - 3fdfffh 4k-word 3fc000h - 3fcfffh 4k-word 3fb000h - 3fbfffh 4k-word 3fa000h - 3fafffh 4k-word plane3 (parameter plane) 3f9000h - 3f9fffh 3f8000h - 3f8fffh plane2 (uniform plane) 0 1 2 3 4 5 12 13 14 15 32k-word 078000h - 07ffffh 32k-word 070000h - 077fffh 32k-word 068000h - 06ffffh 32k-word 060000h - 067fffh 32k-word 058000h - 05ffffh 32k-word 050000h - 057fffh 32k-word plane0 (uniform plane) 048000h - 04ffffh 32k-word 040000h - 047fffh 32k-word 038000h - 03ffffh 32k-word 030000h - 037fffh 32k-word 028000h - 02ffffh 32k-word 020000h - 027fffh 32k-word 018000h - 01ffffh 32k-word 010000h - 017fffh 32k-word 008000h - 00ffffh 32k-word 000000h - 007fffh 0f8000h - 0fffffh 0f0000h - 0f7fffh 0e8000h - 0effffh 0e0000h - 0e7fffh 0d8000h - 0dffffh 0d0000h - 0d7fffh plane1 (uniform plane) 0c8000h - 0cffffh 0c0000h - 0c7fffh 0b8000h - 0bffffh 0b0000h - 0b7fffh 0a8000h - 0affffh 0a0000h - 0a7fffh 098000h - 09ffffh 090000h - 097fffh 088000h - 08ffffh 080000h - 087fffh block number address range block number address range 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 16 18 19 20 21 22 23 17 24 25 6 8 9 10 11 7 26 28 29 30 31 27 62 63 32 33 34 35 42 43 44 45 32k-word 178000h - 17ffffh 32k-word 170000h - 177fffh 32k-word 168000h - 16ffffh 32k-word 160000h - 167fffh 32k-word 158000h - 15ffffh 32k-word 150000h - 157fffh 32k-word 148000h - 14ffffh 32k-word 140000h - 147fffh 32k-word 138000h - 13ffffh 32k-word 130000h - 137fffh 32k-word 128000h - 12ffffh 32k-word 120000h - 127fffh 32k-word 118000h - 11ffffh 32k-word 110000h - 117fffh 32k-word 108000h - 10ffffh 32k-word 100000h - 107fffh 1f8000h - 1fffffh 1f0000h - 1f7fffh 1e8000h - 1effffh 1e0000h - 1e7fffh 1d8000h - 1dffffh 1d0000h - 1d7fffh 1c8000h - 1cffffh 1c0000h - 1c7fffh 1b8000h - 1bffffh 1b0000h - 1b7fffh 1a8000h - 1affffh 1a0000h - 1a7fffh 198000h - 19ffffh 190000h - 197fffh 188000h - 18ffffh 180000h - 187fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 46 48 49 50 51 52 53 47 54 55 36 38 39 40 41 37 56 58 59 60 61 57 92 93 94 95 64 65 72 73 74 75 32k-word 278000h - 27ffffh 32k-word 270000h - 277fffh 32k-word 268000h - 26ffffh 32k-word 260000h - 267fffh 32k-word 258000h - 25ffffh 32k-word 250000h - 257fffh 32k-word 248000h - 24ffffh 32k-word 240000h - 247fffh 32k-word 238000h - 23ffffh 32k-word 230000h - 237fffh 32k-word 228000h - 22ffffh 32k-word 220000h - 227fffh 32k-word 218000h - 21ffffh 32k-word 210000h - 217fffh 32k-word 208000h - 20ffffh 32k-word 200000h - 207fffh 2f8000h - 2fffffh 2f0000h - 2f7fffh 2e8000h - 2effffh 2e0000h - 2e7fffh 2d8000h - 2dffffh 2d0000h - 2d7fffh 2c8000h - 2cffffh 2c0000h - 2c7fffh 2b8000h - 2bffffh 2b0000h - 2b7fffh 2a8000h - 2affffh 2a0000h - 2a7fffh 298000h - 29ffffh 290000h - 297fffh 288000h - 28ffffh 280000h - 287fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 76 78 79 80 81 82 83 77 84 85 66 68 69 70 71 67 86 88 89 90 91 87 122 123 124 102 103 104 105 32k-word 378000h - 37ffffh 32k-word 370000h - 377fffh 32k-word 368000h - 36ffffh 32k-word 360000h - 367fffh 32k-word 358000h - 35ffffh 32k-word 350000h - 357fffh 32k-word 348000h - 34ffffh 32k-word 340000h - 347fffh 32k-word 338000h - 33ffffh 32k-word 330000h - 337fffh 32k-word 328000h - 32ffffh 32k-word 320000h - 327fffh 32k-word 318000h - 31ffffh 32k-word 310000h - 317fffh 32k-word 308000h - 30ffffh 32k-word 300000h - 307fffh 3f0000h - 3f7fffh 3e8000h - 3effffh 3e0000h - 3e7fffh 3d8000h - 3dffffh 3d0000h - 3d7fffh 3c8000h - 3cffffh 3c0000h - 3c7fffh 3b8000h - 3bffffh 3b0000h - 3b7fffh 3a8000h - 3affffh 3a0000h - 3a7fffh 398000h - 39ffffh 390000h - 397fffh 388000h - 38ffffh 380000h - 387fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 106 108 109 110 111 112 113 107 114 115 96 98 99 100 101 97 116 118 119 120 121 117 125 126 134 4k-word rev. 2.44 figure 2.1. memory map (top parameter) selected by be 0 #=v il (bank 0)
lhf12fz8 7 6 5 4 3 2 1 0 7 4k-word 007000h - 007fffh 4k-word 006000h - 006fffh 4k-word 005000h - 005fffh 4k-word 004000h - 004fffh 4k-word 003000h - 003fffh 4k-word 002000h - 002fffh 4k-word 001000h - 001fffh 4k-word 000000h - 000fffh plane2 (uniform plane) 92 93 94 95 64 65 72 73 74 75 32k-word 278000h - 27ffffh 32k-word 270000h - 277fffh 32k-word 268000h - 26ffffh 32k-word 260000h - 267fffh 32k-word 258000h - 25ffffh 32k-word 250000h - 257fffh 32k-word 248000h - 24ffffh 32k-word 240000h - 247fffh 32k-word 238000h - 23ffffh 32k-word 230000h - 237fffh 32k-word 228000h - 22ffffh 32k-word 220000h - 227fffh 32k-word 218000h - 21ffffh 32k-word 210000h - 217fffh 32k-word 208000h - 20ffffh 32k-word 200000h - 207fffh 2f8000h - 2fffffh 2f0000h - 2f7fffh 2e8000h - 2effffh 2e0000h - 2e7fffh 2d8000h - 2dffffh 2d0000h - 2d7fffh 2c8000h - 2cffffh 2c0000h - 2c7fffh 2b8000h - 2bffffh 2b0000h - 2b7fffh 2a8000h - 2affffh 2a0000h - 2a7fffh 298000h - 29ffffh 290000h - 297fffh 288000h - 28ffffh 280000h - 287fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 76 78 79 80 81 82 83 77 84 85 66 68 69 70 71 67 86 88 89 90 91 87 plane1 (uniform plane) block number address range 62 63 32 33 34 35 42 43 44 45 32k-word 178000h - 17ffffh 32k-word 170000h - 177fffh 32k-word 168000h - 16ffffh 32k-word 160000h - 167fffh 32k-word 158000h - 15ffffh 32k-word 150000h - 157fffh 32k-word 148000h - 14ffffh 32k-word 140000h - 147fffh 32k-word 138000h - 13ffffh 32k-word 130000h - 137fffh 32k-word 128000h - 12ffffh 32k-word 120000h - 127fffh 32k-word 118000h - 11ffffh 32k-word 110000h - 117fffh 32k-word 108000h - 10ffffh 32k-word 100000h - 107fffh 1f8000h - 1fffffh 1f0000h - 1f7fffh 1e8000h - 1effffh 1e0000h - 1e7fffh 1d8000h - 1dffffh 1d0000h - 1d7fffh 1c8000h - 1cffffh 1c0000h - 1c7fffh 1b8000h - 1bffffh 1b0000h - 1b7fffh 1a8000h - 1affffh 1a0000h - 1a7fffh 198000h - 19ffffh 190000h - 197fffh 188000h - 18ffffh 180000h - 187fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 46 48 49 50 51 52 53 47 54 55 36 38 39 40 41 37 56 58 59 60 61 57 12 13 14 15 32k-word 078000h - 07ffffh 32k-word 070000h - 077fffh 32k-word 068000h - 06ffffh 32k-word 060000h - 067fffh 32k-word 058000h - 05ffffh 32k-word 050000h - 057fffh 32k-word plane0 (parameter plane) 048000h - 04ffffh 32k-word 040000h - 047fffh 32k-word 038000h - 03ffffh 32k-word 030000h - 037fffh 32k-word 028000h - 02ffffh 32k-word 020000h - 027fffh 32k-word 018000h - 01ffffh 32k-word 010000h - 017fffh 32k-word 008000h - 00ffffh 0f8000h - 0fffffh 0f0000h - 0f7fffh 0e8000h - 0effffh 0e0000h - 0e7fffh 0d8000h - 0dffffh 0d0000h - 0d7fffh 0c8000h - 0cffffh 0c0000h - 0c7fffh 0b8000h - 0bffffh 0b0000h - 0b7fffh 0a8000h - 0affffh 0a0000h - 0a7fffh 098000h - 09ffffh 090000h - 097fffh 088000h - 08ffffh 080000h - 087fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 16 18 19 20 21 22 23 17 24 25 8 9 10 11 26 28 29 30 31 27 127 128 129 130 131 132 133 32k-word plane3 (uniform plane) 3f8000h - 3fffffh 122 123 124 102 103 104 105 32k-word 378000h - 37ffffh 32k-word 370000h - 377fffh 32k-word 368000h - 36ffffh 32k-word 360000h - 367fffh 32k-word 358000h - 35ffffh 32k-word 350000h - 357fffh 32k-word 348000h - 34ffffh 32k-word 340000h - 347fffh 32k-word 338000h - 33ffffh 32k-word 330000h - 337fffh 32k-word 328000h - 32ffffh 32k-word 320000h - 327fffh 32k-word 318000h - 31ffffh 32k-word 310000h - 317fffh 32k-word 308000h - 30ffffh 32k-word 300000h - 307fffh 3f0000h - 3f7fffh 3e8000h - 3effffh 3e0000h - 3e7fffh 3d8000h - 3dffffh 3d0000h - 3d7fffh 3c8000h - 3cffffh 3c0000h - 3c7fffh 3b8000h - 3bffffh 3b0000h - 3b7fffh 3a8000h - 3affffh 3a0000h - 3a7fffh 398000h - 39ffffh 390000h - 397fffh 388000h - 38ffffh 380000h - 387fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 106 108 109 110 111 112 113 107 114 115 96 98 99 100 101 97 116 118 119 120 121 117 125 126 134 block number address range rev. 2.44 figure 2.2. memory map (bottom parameter) selected by be 1 #=v il (bank 1)
lhf12fz8 8 notes: 1. the address a 21 -a 16 are shown in below table for reading the manufacturer code, device code, device configuration code and otp data. 2. bank 0 (selected by be 0 #=v il ) has its parameter blocks in the plane3 (the highest address within the bank). bank 1 (selected by be 1 #=v il ) has its parameter blocks in the plane0 (the lowest address within the bank). 3. block address = the beginning location of a block address within the partition to which the read identifier codes/otp command (90h) has been written. dq 15 -dq 2 are reserved for future implementation. 4. pcrc=partition configuration register code. 5. otp-lk=otp block lock configuration. 6. otp=otp block data. 7. when the data within otp block is read, be 0 # must be v il . otp block in bank 1 (selected by be 1 #=v il ) should not be used. notes: 1. the address to read the identifier codes or otp data is dependent on the partition which is selected when writing the read identifier codes/otp command (90h). 2. refer to table 12 for the partition configuration register. 3. when the data within otp block is read, be 0 # must be v il . otp block in bank 1 (selected by be 1 #=v il ) should not be used. table 3. identifier codes and otp address for read operation code address [a 15 -a 0 ] data [dq 15 -dq 0 ] notes manufacturer code manufacturer code 0000h 00b0h 1 device code device code 0001h 00b0h (be 0 #=v il ) 1, 2 00b1h (be 1 #=v il ) block lock configuration code block is unlocked block address + 2 dq 0 = 0 3 block is locked dq 0 = 1 3 block is not locked-down dq 1 = 0 3 block is locked-down dq 1 = 1 3 device configuration code partition configuration register 0006h pcrc 1, 4 otp otp lock 0080h otp-lk 1, 5, 7 otp 0081-0088h otp 1, 6, 7 table 4. identifier codes and otp address for read operation on partition configuration (1) partition configuration register (2) address (3) pcr.10 pcr.9 pcr.8 [a 21 -a 16 ] 0 0 0 00h 0 0 1 00h or 10h 0 1 0 00h or 20h 1 0 0 00h or 30h 0 1 1 00h or 10h or 20h 1 1 0 00h or 20h or 30h 1 0 1 00h or 10h or 30h 1 1 1 00h or 10h or 20h or 30h rev. 2.44
lhf12fz8 9 rev. 2.44 customer programmable area lock bit (dq 1 ) factory programmed area lock bit (dq 0 ) customer programmable area factory programmed area reserved for future implementation 000080h 000081h 000084h 000085h 000088h [a 21 -a 0 ] (dq 15 -dq 2) figure 3. otp block address map for otp program (1) (the area outside 80h~88h cannot be used.) note: 1. when the otp program operation is exec uted, write the otp program command with be 0 # at v il . otp block in bank 1 (selected by be 1 #=v il ) should not be used.
lhf12fz8 10 rev. 2.44 notes: 1. refer to dc characteristics. when v pp v pplk , memory contents can be read, but cannot be altered. 2. x can be v il or v ih for control pins and addresses, and v pplk or v pph1/2 for v pp . see dc characteristics for v pplk and v pph1/2 voltages. 3. rst# at gnd0.2v ensures the lowest power consumption. 4. command writes involving block erase, (page buffer) program or otp program are reliably executed when v pp =v pph1/2 and v cc =2.7v-3.6v. command writes involving bank erase are reliably executed when v pp =v pph1 and v cc =2.7v-3.6v. 5. refer to table 6 for valid d in during a write operation. 6. never hold oe# low and we# low at the same timing. 7. refer to appendix of lh28f128bf series for more information about query code. 8. while the erase or program operation is executed in one ba nk, it is inhibited to execute the erase or program operation in another bank. 9. when the data within otp block is read, be 0 # must be v il . otp block in bank 1 (selected by be 1 #=v il ) should not be used. table 5. bus operation (1, 2) mode notes rst# be 0 #be 1 #oe#we#address v pp dq 0-15 read array bank 0 6 v ih v il v ih v il v ih xx d out bank 1 v ih v il inhibited v il v il n/a output disable v ih v il v il v ih v ih xxhigh z standby bank 0 v ih v ih v il xxxxhigh z bank 1 v il v ih bank 0, 1 v ih v ih reset 3 v il xxxx x xhigh z read identifier codes/otp bank 0 6,9 v ih v il v ih v il v ih see table 3 and table 4 x see table 3 and table 4 bank 1 v ih v il inhibited v il v il n/a read query bank 0 6,7 v ih v il v ih v il v ih see appendix x see appendix bank 1 v ih v il inhibited v il v il n/a write bank 0 4,5, 6,8 v ih v il v ih v ih v il xx d in bank 1 v ih v il inhibited v il v il n/a
lhf12fz8 11 notes: 1. bus operations are defined in table 5. 2. all addresses which are written at the first bus cycle should be the same as the addresses which are written at the second bus cycle. x=any valid address. bank erase is executed to the bank selected by be 0 # or be 1 #. pa=address within the selected partition. ia=identifier codes address (see table 3 and table 4). qa=query codes address. refer to appendix of lh28f128bf series for details. ba=address within the block being erased, set/cleared block lock bit or set block lock-down bit. wa=address of memory location for the program command or the first address for the page buffer program command. oa=address of otp block to be read or programmed (see figure 3). pcrc=partition configuration register code presented on the address a 0 -a 15 . 3. id=data read from identifier codes. (see table 3 and table 4). qd=data read from query database. refer to appendix of lh28f128bf series for details. srd=data read from status register. see table 10 and table 11 for a description of the status register bits. wd=data to be programmed at location wa. data is latched on the rising edge of we# or be 0 # or be 1 # (whichever goes high first) during command write cycles. od=data within otp block. data is latched on the rising edge of we# or be 0 # or be 1 # (whichever goes high first) during command write cycles. n-1=n is the number of the words to be loaded into a page buffer. 4. following the read identifier codes/otp command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code and the data within otp block (see table 3 and table 4). the read query command is available for read ing cfi (common flash interface) information. 5. block erase, bank erase or (page buffer) program cannot be executed when the selected bl ock is locked. unlocked block can be erased or programmed when rst# is v ih . 6. either 40h or 10h are recognized by the cui (command user interface) as the program setup. 7. following the third bus cycle, input the program sequential address and write data of "n" times. finally, input the any valid address within the target block to be programmed and the confirm command (d0h). refer to appendix of table 6. command definitions (12) command bus cycles req?d notes first bus cycle second bus cycle oper (1) addr (2) data oper (1) addr (2) data (3) read array 1 write pa ffh read identifier codes/otp 2 4,11 write pa 90h read ia or oa id or od read query 2 4 write pa 98h read qa qd read status register 2 write pa 70h read pa srd clear status register 1 write pa 50h block erase 2 5 write ba 20h write ba d0h bank erase 2 5,9 write x 30h write x d0h program 2 5,6 write wa 40h or 10h write wa wd page buffer program 4 5,7 write wa e8h write wa n-1 block erase and (page buffer) program suspend 1 8,9 write pa b0h block erase and (page buffer) program resume 1 8,9 write pa d0h set block lock bit 2 write ba 60h write ba 01h clear block lock bit 2 10 write ba 60h write ba d0h set block lock-down bit 2 write ba 60h write ba 2fh otp program 2 9,11 write oa c0h write oa od set partition configuration register 2 write pcrc 60h write pcrc 04h rev. 2.44
lhf12fz8 12 lh28f128bf series for details. 8. if the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and th en the suspended erase operation should be resumed next. 9. bank erase and otp program operations can not be suspended. the otp program command can not be accepted while the block erase operation is being suspended. 10. following the clear block lock bit command, block which is not locked-down is unlocked when wp# is v il . when wp# is v ih , lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. when the data within otp block is read, be 0 # must be v il . when the otp program operatio n is executed, write the otp program command with be 0 # at v il . otp block in bank 1 (selected by be 1 #=v il ) should not be used. 12. commands other than those shown above are reserved by sharp for future device implementations and should not be used. rev. 2.44
lhf12fz8 13 notes: 1. dq 0 =1: a block is locked; dq 0 =0: a block is unlocked. dq 1 =1: a block is locked-down; dq 1 =0: a block is not locked-down. 2. erase and program are general terms, respectively, to express: block erase, bank erase and (page buffer) program operations. 3. at power-up or device reset, all blocks default to locked state and are no t locked-down, that is, [001] (wp#=0) or [101] (wp#=1), regardless of the states before power-off or reset operation. 4. when wp# is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 5. otp (one time program) block has the lock function which is different from those described above. notes: 1. "set lock" means set block lock bit comma nd, "clear lock" means clear block lock bit command and "set lock-down" means set block lock-down bit command. 2. when the set block lock-down bit command is written to the unlocked block (dq 0 =0), the corresponding block is locked-down and automatically locked at the same time. 3. "no change" means that the state remains unchanged after the command written. 4. in this state transitions table, assu mes that wp# is not changed and fixed v il or v ih . table 7. functions of block lock (5) and block lock-down current state erase/program allowed (2) state wp# dq 1 (1) dq 0 (1) state name [000] 0 0 0 unlocked yes [001] (3) 00 1locked no [011] 0 1 1 locked-down no [100] 1 0 0 unlocked yes [101] (3) 10 1locked no [110] (4) 1 1 0 lock-down disable yes [111] 1 1 1 lock-down disable no table 8. block locking state transitions upon command write (4) current state result after lock command written (next state) state wp# dq 1 dq 0 set lock (1) clear lock (1) set lock-down (1) [000] 0 0 0 [001] no change [011] (2) [001] 0 0 1 no change (3) [000] [011] [011] 0 1 1 no change no change no change [100] 1 0 0 [101] no change [111] (2) [101] 1 0 1 no change [100] [111] [110] 1 1 0 [111] no change [111] (2) [111] 1 1 1 no change [110] no change rev. 2.44
lhf12fz8 14 rev. 2.44 notes: 1. "wp#=0 1" means that wp# is driven to v ih and "wp#=1 0" means that wp# is driven to v il . 2. state transition from the current state [011] to the next state depends on the previous state. 3. when wp# is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 4. in this state transitions table, assumes that lock configuration commands are not written in previous, current and next state. table 9. block locking state transitions upon wp# transition (4) previous state current state result after wp# transition (next state) state wp# dq 1 dq 0 wp#=0 1 (1) wp#=1 0 (1) - [000] 0 0 0 [100] - - [001] 0 0 1 [101] - [110] (2) [011] 0 1 1 [110] - other than [110] (2) [111] - - [100] 1 0 0 - [000] - [101] 1 0 1 - [001] -[110]110 - [011] (3) - [111] 1 1 1 - [011]
lhf12fz8 15 table 10. status register definition rrrrrrrr 15 14 13 12 11 10 9 8 wsms bess befces pbpops vpps pbpss dps r 76543210 sr.15 - sr.8 = reserved for future enhancements (r) sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = block erase suspend status (bess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = block erase and bank erase status (befces) 1 = error in block erase or bank erase 0 = successful block erase or bank erase sr.4 = (page buffer) program and otp program status (pbpops) 1 = error in (page buffer) program or otp program 0 = successful (page buffer) program or otp program sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok sr.2 = (page buffer) program suspend status (pbpss) 1 = (page buffer) program suspended 0 = (page buffer) program in progress/completed sr.1 = device protect status (dps) 1 = erase or program attempted on a locked block, operation abort 0 = unlocked sr.0 = reserved for future enhancements (r) notes: status register indicates the status of the partition, not wsm (write state machine). even if the sr.7 is "1", the wsm may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. check sr.7 to determine block erase, bank erase, (page buffer) program or otp program completion. sr.6 - sr.1 are invalid while sr.7="0". if both sr.5 and sr.4 are "1"s after a block erase, bank erase, (page buffer) program, set/clear block lock bit, set block lock-down bit, set partition configuration register attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after block erase, bank erase, (page buffer) program or otp program command sequences. sr.3 is not guaranteed to report accurate feedback when v pp v pph1 , v pph2 or v pplk . sr.1 does not provide a continuous indication of block lock bit. the wsm interrogates the block lock bit only after block erase, bank erase, (page buffer) program or otp program command sequences. it informs the system, depending on the attempted operation, if the block lock bit is set. reading the block lock configuration codes after writing the read identifier codes/otp command indicates block lock bit status. sr.15 - sr.8 and sr.0 are rese rved for future use and should be masked out when polling the status register. rev. 2.44
lhf12fz8 16 rev. 2.44 table 11. extended status register definition rrrrrrrr 15 14 13 12 11 10 9 8 smsrrrrrrr 76543210 xsr.15-8 = reserved for future enhancements (r) xsr.7 = state machine status (sms) 1 = page buffer program available 0 = page buffer program not available xsr.6-0 = reserved for future enhancements (r) notes: after issue a page buffer program command (e8h), xsr.7="1" indicates that the entered command is accepted. if xsr.7 is "0", the command is not accepted and a next page buffer program command (e8h) should be issued again to check if page buffer is available or not. xsr.15-8 and xsr.6-0 are reserved for future use and should be masked out when polling the extended status register.
lhf12fz8 17 rev. 2.44 table 12. partition configuration register definition rrrrrpc2pc1pc0 15 14 13 12 11 10 9 8 rrrrrrrr 76543210 pcr.15-11 = reserved for future enhancements (r) pcr.10-8 = partition configuration (pc2-0) 000 = no partitioning. dual work is not allowed. 001 = plane1-3 are merged into one partition. (default in bank 1 selected by be 1 #=v il ) 010 = plane 0-1 and plane2-3 are merged into one partition respectively. 100 = plane 0-2 are merged into one partition. (default in bank 0 selected by be 0 #=v il ) 011 = plane 2-3 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. 110 = plane 0-1 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. 101 = plane 1-2 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. 111 = there are four partitions in this configuration. each plane corresponds to each partition respec- tively. dual work operation is available between any two partitions. pcr.7-0 = reserved for future enhancements (r) notes: after power-up or device reset, pcr10-8 (pc2-0) is set to "001" in bank 1 and "100" in bank 0. see figure 4 for the detail on partition configuration. pcr.15-11 and pcr.7-0 are reserved for future use and should be masked out when checking the partition configuration register. plane1 plane0 plane2 plane3 partition1 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 partition1 partition1 partition0 plane1 plane0 plane2 plane3 partition1 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 partition1 partition1 partition0 partition2 partition3 partition2 partition2 partition1 partition2 000 001 010 100 011 110 101 111 pc2 pc1pc0 partitioning for dual work partitioning for dual work pc2 pc1pc0 figure 4. partition configuration
lhf12fz8 18 1 electrical specifications 1.1 absolute maximum ratings * operating temperature during read, erase and program ...-40 c to +85 c (1) storage temperature during under bias............................... -40 c to +85 c during non bias................................ -65 c to +125 c voltage on any pin (except v cc and v pp ).............. -0.5v to v cc +0.5v (2) v cc supply voltage ........................... -0.2v to +3.9v (2) v pp supply voltage .................... -0.2v to +12.6v (2, 3, 4) output short circuit current ........................... 100ma (5) *warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. notes: 1. operating temperature is for extended temperature product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is -0.5v on input/output pins and -0.2v on v cc and v pp pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/output pins is v cc +0.5v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 3. maximum dc voltage on v pp may overshoot to +13.0v for periods <20ns. 4. v pp erase/program voltage is normally 2.7v-3.6v. applying 11.7v-12.3v to v pp during erase/program can be done for a maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks. v pp may be connected to 11.7v-12.3v for a total of 80 hours maximum. 5. output shorted for no more than one second. no more than one output shorted at a time. rev. 2.44 1.2 operating conditions notes: 1. see dc characteristics tables for voltage range-specific specification. 2. applying v pp =11.7v-12.3v during a erase or program can be done for a maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks. a permanent connection to v pp =11.7v-12.3v is not allowed and can cause damage to the device. parameter symbol min. typ. max. unit notes operating temperature t a -40 +25 +85 c v cc supply voltage v cc 2.7 3.0 3.6 v 1 v pp voltage when used as a logic control v pph1 1.65 3.0 3.6 v 1 v pp supply voltage v pph2 11.7 12 12.3 v 1, 2 main block erase cycling: v pp =v pph1 100,000 cycles parameter block erase cycling: v pp =v pph1 100,000 cycles main block erase cycling: v pp =v pph2 , 80 hrs. 1,000 cycles parameter block erase cycling: v pp =v pph2 , 80 hrs. 1,000 cycles maximum v pp hours at v pph2 80 hours
lhf12fz8 19 test points v cc /2 v cc /2 input v cc 0.0 output ac test inputs are driven at v cc (min) for a logic "1" and 0.0v for a logic "0". input timing begins, and output timing ends at v cc /2. input rise and fall times (10% to 90%) < 5ns. worst case speed conditions are when v cc =v cc (min).

! " figure 6. transient equivalent testing load circuit rev. 2.44 table 13. configuration capacitance loading value test configuration c l (pf) v cc =2.7v-3.6v 50 1.2.2 ac input/output test conditions 1.2.1 capacitance (1) (t a = + 25 c, f=1mhz) note: 1. sampled, not 100% tested. parameter symbol condition min. typ. max. unit input capacitance c in v in =0.0v 12 16 pf output capacitance c out v out =0.0v 20 24 pf figure 5. transient input/output reference waveform for v cc =2.7v-3.6v
lhf12fz8 20 rev. 2.44 1.2.3 dc characteristics v cc =2.7v-3.6v symbol parameter notes min. typ. max. unit test conditions i li input load current 1 -2.0 +2.0 a v cc =v cc max., v in /v out =v cc or gnd i lo output leakage current 1 -2.0 +2.0 a i ccs v cc standby current 1840 a v cc =v cc max., be 0 #=be 1 #=rst#= v cc 0.2v, wp#=v cc or gnd i ccas v cc automatic power savings current 1,4 8 40 a v cc =v cc max., be 0 # or be 1 #= gnd0.2v, wp#=v cc or gnd i ccd v cc reset power-down current 1840 a rst#=gnd0.2v i ccr average v cc read current normal mode 1,7 15 25 ma v cc =v cc max., be 0 # or be 1 #=v il , oe#=v ih , f=5mhz average v cc read current page mode 8 word read 1,7 5 10 ma i ccw v cc (page buffer) program current 1,5,7 20 60 ma v pp =v pph1 1,5,7 10 20 ma v pp =v pph2 i cce v cc block erase, bank erase current 1,5,7 10 30 ma v pp =v pph1 1,5,7 10 30 ma v pp =v pph2 i ccws i cces v cc (page buffer) program or block erase suspend current 1,2,7 10 200 a be 0 #=be 1 #=v ih i pps i ppr v pp standby or read current 1,6,7 4 10 a v pp v cc i ppw v pp (page buffer) program current 1,5,6,7 2 5 a v pp =v pph1 1,5,6,7 10 30 ma v pp =v pph2 i ppe v pp block erase, bank erase current 1,5,6,7 2 5 a v pp =v pph1 1,5,6,7 5 15 ma v pp =v pph2 i ppws v pp (page buffer) program suspend current 1,6,7 2 5 a v pp =v pph1 1,6,7 10 200 a v pp =v pph2 i ppes v pp block erase suspend current 1,6,7 2 5 a v pp =v pph1 1,6,7 10 200 a v pp =v pph2
lhf12fz8 21 notes: 1. all currents are in rms unless otherwise noted . typical values are the reference values at v cc =3.0v and t a =+25 c unless v cc is specified. 2. i ccws and i cces are specified with the device de-selected. if read or (page buffer) program is executed while in block erase suspend mode, the device?s current draw is the sum of i cces and i ccr or i ccw . if read is executed while in (page buffer) program suspend mode, the device?s current draw is the sum of i ccws and i ccr . 3. block erase, bank erase, (page buffer) program and otp program are inhibited when v pp v pplk , and not guaranteed in the range between v pplk (max.) and v pph1 (min.), between v pph1 (max.) and v pph2 (min.) and above v pph2 (max.). 4. the automatic power savings (aps) feature automatically places the device in power save mode after read cycle completion. standard address access timings (t av q v ) provide new data when addresses are changed. 5. sampled, not 100% tested. 6. v pp is not used for power supply pin. with v pp v pplk , block erase, bank erase, (page buffer) program and otp program cannot be executed and should not be attempted. applying 12v0.3v to v pp provides fast erasing or fast programming mode. in this mode, v pp is power supply pin and supplies the memory cell current for block erasing and (p age buffer) programming. use similar power supply trace widths and layout considerations given to the v cc power bus. applying 12v0.3v to v pp during erase/program can only be done for a maximum of 1,000 cycles on each block. v pp may be connected to 12v0.3v for a total of 80 hours maximum. 7. the operating current in dual work is the sum of th e operating current (read, eras e, program) in each plane. v il input low voltage 5 -0.4 0.4 v v ih input high voltage 5 2.4 v cc + 0.4 v v ol output low voltage 5 0.2 v v cc =v cc min., i ol =100 a v oh output high voltage 5 v cc -0.2 v v cc =v cc min., i oh =-100a v pplk v pp lockout during normal operations 3,5,6 0.4 v v pph1 v pp during block erase, bank erase, (page buffer) program or otp program operations 6 1.65 3.0 3.6 v v pph2 v pp during block erase, (page buffer) program or otp program operations 6 11.7 12 12.3 v v lko v cc lockout voltage 1.5 v v cc =2.7v-3.6v symbol parameter notes min. typ. max. unit test conditions rev. 2.44 dc characteristics (continued)
lhf12fz8 22 1.2.4 ac characteristics - read-only operations (1) notes: 1. see ac input/output reference waveform for timing measurements and maximum allowable input slew rate. 2. sampled, not 100% tested. 3. oe# may be delayed up to t elqv ? t glqv after the falling edge of be 0 # or be 1 # without impact to t elqv . 4. address setup time (t av e l , t av g l ) is defined from the falling edge of be 0 # or be 1 # or oe# (whichever goes low last). 5. address hold time (t elax , t glax ) is defined from the falling edge of be 0 # or be 1 # or oe# (whichever goes low last). 6. specifications t av e l , t av g l , t elax , t glax and t ehel , t ghgl for read operations apply to only status register read operations. v cc =2.7v-3.6v, t a =-40 c to +85 c symbol parameter notes min. max. unit t avav read cycle time 90 ns t avqv address to output delay 90 ns t elqv be 0 # or be 1 # to output delay 390ns t apa page address access time 35 ns t glqv oe# to output delay 3 20 ns t phqv rst# high to output delay 150 ns t ehqz , t ghqz be 0 # or be 1 # or oe# to output in high z, whichever occurs first 220ns t elqx be 0 # or be 1 # to output in low z 20 ns t glqx oe# to output in low z 2 0 ns t oh output hold from first occurring address, be 0 # or be 1 # or oe# change 20 ns t av e l , t avgl address setup to be 0 # or be 1 #, oe# going low for reading status register 4, 6 10 ns t elax , t glax address hold from be 0 # or be 1 #, oe# going low for reading status register 5, 6 30 ns t ehel , t ghgl be 0 # or be 1 #, oe# pulse width high for reading status register 630 ns rev. 2.44
lhf12fz8 23 t avqv t ehqz t ghqz t elqv t phqv t glqv t oh v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il (p) (d/q) (w) (g) (e) (a) a 20-0 dq 15-0 ce# oe# we# rst# high z t elqx valid output valid address t avav t glqx t ghgl t ehel t avel t avgl t glax t elax t oh a 21-0 (a) be 0 # or be 1 # (e) figure 7. ac waveform for single asynchronous read operations from status register, identifier codes, otp block or query code rev. 2.44
lhf12fz8 24 t avqv t elqv t ehqz t ghqz t oh t apa t glqv t phqv high z v ih v il v ih v il v ih v il v ih v il v ih v il (p) (w) (g) (e) (a) a 20-3 v ih v il (a) a 2-0 v oh v ol (d/q) dq 15-0 ce# oe# we# rst# t glqx t elqx valid address valid address valid address valid address valid output valid output valid output valid output valid address a 21-3 (a) figure 8. ac waveform for asynchronous page mode read operations from main blocks or parameter blocks rev. 2.44 be 0 # or be 1 # (e)
lhf12fz8 25 rev. 2.44 1.2.5 ac characteristics - write operations (1), (2) notes: 1. the timing characteristics for reading th e status register during block erase, ba nk erase, (page buffer) program and otp program operations are the same as during read-only operatio ns. refer to ac characteristics for read-only operations. 2. a write operation can be initiated and terminated with either be 0 # or be 1 # or we#. 3. sampled, not 100% tested. 4. write pulse width (t wp ) is defined from the falling edge of be 0 # or be 1 # or we# (whichever goes low last) to the rising edge of be 0 # or be 1 # or we# (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . 5. write pulse width high (t wph ) is defined from the rising edge of be 0 # or be 1 # or we# (whichever goes high first) to the falling edge of be 0 # or be 1 # or we# (whichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 6. v pp should be held at v pp =v pph1/2 until determination of block erase, (page buffer) program or otp program success (sr.1/3/4/5=0) and held at v pp =v pph1 until determination of bank erase success (sr.1/3/5=0). 7. t whr0 (t ehr0 ) after the read query or read identifier codes/otp command=t avqv +100ns. 8. refer to table 6 for valid address and data for block erase, bank erase, (page buffer) program, otp program or lock bit configuration. v cc =2.7v-3.6v, t a =-40 c to +85 c symbol parameter notes min. max. unit t avav write cycle time 90 ns t phwl (t phel ) rst# high recovery to we# ( be 0 # or be 1 # ) going low 3150 ns t elwl (t wlel ) be 0 # or be 1 # (we#) setup to we# (be 0 # or be 1 #) going low 0ns t wlwh (t eleh )we# (be 0 # or be 1 #) pulse width 460 ns t dvwh (t dveh ) data setup to we# (be 0 # or be 1 #) going high 840 ns t av w h (t av e h ) address setup to we# (be 0 # or be 1 #) going high 850 ns t wheh (t ehwh ) be 0 # or be 1 # (we#) hold from we# (be 0 # or be 1 #) high 0ns t whdx (t ehdx ) data hold from we# (be 0 # or be 1 #) high 0ns t whax (t ehax ) address hold from we# (be 0 # or be 1 #) high 0ns t whwl (t ehel )we# (be 0 # or be 1 #) pulse width high 530 ns t shwh (t sheh ) wp# high setup to we# (be 0 # or be 1 #) going high 30 ns t vvwh (t vveh )v pp setup to we# (be 0 # or be 1 #) going high 3200 ns t whgl (t ehgl ) write recovery before read 30 ns t qvsl wp# high hold from valid srd 3, 6 0 ns t qvvl v pp hold from valid srd 3, 6 0 ns t whr0 (t ehr0 )we# (be 0 # or be 1 #) high to sr.7 going "0" 3, 7 t av q v + 50 ns
lhf12fz8 26 t avav t avwh (t aveh ) t whax (t ehax ) t elwl (t wlel ) t phwl (t phel ) t wlwh t whwl (t ehel ) t whdx (t ehdx ) t dvwh (t dveh ) t shwh (t sheh ) t vvwh (t vveh ) t whqv1,2,3 (t ehqv1,2,3 ) t qvsl t qvvl t wheh (t ehwh )t whgl (t ehgl ) v ih v il v ih v il v ih v il v ih v il v ih v il (d/q) (w) (g) (e) (a) notes 5, 6 a 20-0 dq 15-0 (v) v pp v ih v pph1,2 v pplk v il v il (p) rst# ce# oe# we# v ih v il (s) wp# (t eleh ) note 1 note 2 note 3 note 4 note 5 valid address valid address valid address data in data in valid srd notes: 1. v cc power-up and standby. 2. write each first cycle command. 3. write each second cycle command or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. for read operation, oe# and ce# must be driven active, and we# de-asserted. "1" "0" (r) sr.7 t whr0 (t ehr0 ) notes 5, 6 a 21-0 (a) 6. for read operation, oe# and be 0 # or be 1 # must be driven active, and we# de-asserted. figure 9. ac waveform for write operations rev. 2.44 be 0 # or be 1 # (e)
lhf12fz8 27 abort complete t plph t plph t 2vph t plrh t phqv t phqv (a) reset during read array mode (b) reset during erase or program mode (c) rst# rising timing rst# rst# v il v ih v il v ih v cc gnd v cc (min) rst# v il v ih sr.7="1" v oh v ol (d/q) dq 15-0 valid output high z (p) (p) (p) v oh v ol (d/q) dq 15-0 valid output high z v oh v ol (d/q) dq 15-0 valid output high z t phqv t vhqv notes: 1. a reset time, t phqv , is required from the later of sr.7 going "1" or rst# going high until outputs are valid. refer to ac characteristics - read-only operations for t phqv . 2. t plph is <100ns the device may still reset but this is not guaranteed. 3. sampled, not 100% tested. 4. if rst# asserted while a block erase, bank erase, (page buffer) program or otp program operation is not executing, the reset will complete within 100ns. 5. when the device power-up, holding rst# low minimum 100ns is required after v cc has been in predefined range and also has been in stable there. reset ac specifications (v cc =2.7v-3.6v, t a =-40 c to +85 c) symbol parameter notes min. max. unit t plph rst# low to reset during read (rst# should be low during power-up.) 1, 2, 3 100 ns t plrh rst# low to reset during erase or program 1, 3, 4 22 s t 2vph v cc 2.7v to rst# high 1, 3, 5 100 ns t vhqv v cc 2.7v to output delay 31ms figure 10. ac waveform for reset operations rev. 2.44 1.2.6 reset operations
lhf12fz8 28 rev. 2.44 1.2.7 block erase, bank erase, (page buff er) program and otp program performance (3) notes: 1. typical values measured at v cc =3.0v, v pp =3.0v or 12v, and t a =+25 c. assumes corresponding lock bits are not set. subject to change based on device characterization. 2. excludes external system-level overhead. 3. sampled, but not 100% tested. 4. a latency time is required from writing suspend command (we# or be 0 # or be 1 # going high) until sr.7 going "1". 5. if the interval time from a block erase resume comma nd to a subsequent block erase suspend command is shorter than t eres and its sequence is repeated, the block erase operation may not be finished. 6. when the otp program operation is executed, write the otp program command with be 0 # at v il . otp block in bank 1 (selected by be 1 #=v il ) should not be used. v cc =2.7v-3.6v, t a =-40 c to +85 c symbol parameter notes page buffer command is used or not used v pp =v pph1 (in system) v pp =v pph2 (in manufacturing) unit min. typ. (1) max. (2) min. typ. (1) max. (2) t wpb 4k-word parameter block program time 2 not used 0.05 0.3 0.04 0.12 s 2 used 0.03 0.12 0.02 0.06 s t wmb 32k-word main block program time 2 not used 0.38 2.4 0.31 1.0 s 2 used 0.24 1.0 0.17 0.5 s t whqv1 / t ehqv1 word program time 2 not used 11 200 9 185 s 2 used 7 100 5 90 s t whov1 / t ehov1 otp program time 2, 6 not used 36 400 27 185 s t whqv2 / t ehqv2 4k-word parameter block erase time 2 - 0.3 4 0.2 4 s t whqv3 / t ehqv3 32k-word main block erase time 2 - 0.6 5 0.5 5 s bank erase time 2 80 700 66 700 s t whrh1 / t ehrh1 (page buffer) program suspend latency time to read 4- 510 510 s t whrh2 / t ehrh2 block erase suspend latency time to read 4- 520 520 s t eres latency time from block erase resume command to block erase suspend command 5-500 500 s
lhf12fz8 29 rev. 2.44 2 related document information (1) note: 1. international customers should contact their local sharp or distribution sales offices. document no. document name fum00701 lh28f128bf series appendix

rev. 1.10 i a-1 recommended operating conditions a-1.1 at device power-up ac timing illustrated in figure a-1 is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a-1. ac timing at device power-up for the ac specifications t vr , t r , t f in the figure, refer to the next page. see the ?electrical specifications? described in specifications for the supply voltage range, the operating temperature and the ac specifications not shown in the next page. t 2vph v cc gnd v cc (min) rp# v il v ih (p) t phqv v ccw *1 gnd v ccwh1/2 (v) ce# v il v ih (e) we# v il v ih (w) oe# v il v ih (g) wp# v il v ih (s) v oh v ol (d/q) data high z valid output t vr t f t elqv t f t glqv (a) address valid (rst#) (v pp ) t r or t f address v il v ih t avqv t r or t f t r t r *1 to prevent the unwanted writes, system designers should consider the design, which applies v ccw (v pp ) to 0v during read operations and v ccwh1/2 (v pph1/2 ) during write or erase operations. (v pph1/2 ) see the application note ap-007-sw-e for details. be 0 # or be 1 # (e)
rev. 1.10 ii a-1.1.1 rise and fall time notes: 1. sampled, not 100% tested. 2. this specification is applied for not only the device power-up but also the normal operations. symbol parameter notes min. max. unit t vr v cc rise time 1 0.5 30000 s/v t r input signal rise time 1, 2 1 s/v t f input signal fall time 1, 2 1 s/v
rev. 1.10 iii a-1.2 glitch noises do not input the glitch noises which are below v ih (min.) or above v il (max.) on address, data, reset, and control signals, as shown in figure a-2 (b). the acceptable glitch noises are illustrated in figure a-2 (a). figure a-2. waveform for glitch noises see the ? dc characteristics ? described in specifications for v ih (min.) and v il (max.). (a) acceptable glitch noises input signal v ih (min.) input signal v ih (min.) input signal v il (max.) input signal v il (max.) (b) not acceptable glitch noises
rev. 1.10 iv a-2 related document information (1) note: 1. international customers should contact their local sharp or distribution sales office. document no. document name ap-001-sd-e flash memory family software drivers ap-006-pt-e data protection method of sharp flash memory ap-007-sw-e rp#, v pp electric potential switching circuit
v a-3 status register read operations if ac timing for reading the status register described in specifications is not satisfied, a system processor can check the status register bit sr.15 instead of sr.7 to determine when the erase or program operation has been completed. figure a-3-1. example of checking the status register (in this example, the device contains four partitions.) table a-3-1. status register definition (sr.15 and sr.7) sr.15 = write state machine status: (dq 15 ) 1 = ready in all partitions 0 = busy in any partition sr.7 = write state machine status for each partition: (dq 7 ) 1 = ready in the addressed partition 0 = busy in the addressed partition notes: sr.15 indicates the status of wsm (write state machine). if sr.15="0", erase or program operation is in progress in any partition. sr.7 indicates the status of the partition. if sr.7="0", erase or program operation is in progress in the addressed partition. even if the sr.7 is "1", the wsm may be occupied by the other partition. v ih v il v ih v il v ih v il v ih v il (d/q) (w) (e) (a) address dq 15-0 ce# we# valid address within partition 0 valid command "1" "0" (r) sr.15 ( partition 0 ) "1" "0" (r) sr.7 ( partition 0 ) "1" "0" (r) sr.15 ( partition 1 ) "1" "0" (r) sr.7 ( partition 1 ) "1" "0" (r) sr.15 ( partition 2 ) "1" "0" (r) sr.7 ( partition 2 ) "1" "0" (r) sr.15 ( partition 3 ) "1" "0" (r) sr.7 ( partition 3 ) plane1 plane0 plane2 plane3 partition0 partition1 partition2 partition3 operation to partition 0 t whr0 (t ehr0 ) valid address within partition 2 valid command operation to partition 2 t whr0 (t ehr0 ) check sr.15 instead of sr.7 in partition 0 check sr.15 instead of sr.7 in partition 2 021211
s p e c i f i c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e . s u g g e s t e d a p p l i c a t i o n s ( i f a n y ) a r e f o r s t a n d a r d u s e ; s e e i m p o r t a n t r e s t r i c t i o n s f o r l i m i t a t i o n s o n s p e c i a l a p p l i c a t i o n s . s e e l i m i t e d w a r r a n t y f o r s h a r p ? s p r o d u c t w a r r a n t y . t h e l i m i t e d w a r r a n t y i s i n l i e u , a n d e x c l u s i v e o f , a l l o t h e r w a r r a n t i e s , e x p r e s s o r i m p l i e d . a l l e x p r e s s a n d i m p l i e d w a r r a n t i e s , i n c l u d i n g t h e w a r r a n t i e s o f m e r c h a n t a b i l i t y , f i t n e s s f o r u s e a n d f i t n e s s f o r a p a r t i c u l a r p u r p o s e , a r e s p e c i f i c a l l y e x c l u d e d . i n n o e v e n t w i l l s h a r p b e l i a b l e , o r i n a n y w a y r e s p o n s i b l e , f o r a n y i n c i d e n t a l o r c o n s e q u e n t i a l e c o n o m i c o r p r o p e r t y d a m a g e . n o r t h a m e r i c a e u r o p e j a p a n s h a r p m i c r o e l e c t r o n i c s o f t h e a m e r i c a s 5 7 0 0 n w p a c i f i c r i m b l v d . c a m a s , w a 9 8 6 0 7 , u . s . a . p h o n e : ( 1 ) 3 6 0 - 8 3 4 - 2 5 0 0 f a x : ( 1 ) 3 6 0 - 8 3 4 - 8 9 0 3 f a s t i n f o : ( 1 ) 8 0 0 - 8 3 3 - 9 4 3 7 w w w . s h a r p s m a . c o m s h a r p m i c r o e l e c t r o n i c s e u r o p e d i v i s i o n o f s h a r p e l e c t r o n i c s ( e u r o p e ) g m b h s o n n i n s t r a s s e 3 2 0 0 9 7 h a m b u r g , g e r m a n y p h o n e : ( 4 9 ) 4 0 - 2 3 7 6 - 2 2 8 6 f a x : ( 4 9 ) 4 0 - 2 3 7 6 - 2 2 3 2 w w w . s h a r p s m e . c o m s h a r p c o r p o r a t i o n e l e c t r o n i c c o m p o n e n t s & d e v i c e s 2 2 - 2 2 n a g a i k e - c h o , a b e n o - k u o s a k a 5 4 5 - 8 5 2 2 , j a p a n p h o n e : ( 8 1 ) 6 - 6 6 2 1 - 1 2 2 1 f a x : ( 8 1 ) 6 1 1 7 - 7 2 5 3 0 0 / 6 1 1 7 - 7 2 5 3 0 1 w w w . s h a r p - w o r l d . c o m t a i w a n s i n g a p o r e k o r e a s h a r p e l e c t r o n i c c o m p o n e n t s ( t a i w a n ) c o r p o r a t i o n 8 f - a , n o . 1 6 , s e c . 4 , n a n k i n g e . r d . t a i p e i , t a i w a n , r e p u b l i c o f c h i n a p h o n e : ( 8 8 6 ) 2 - 2 5 7 7 - 7 3 4 1 f a x : ( 8 8 6 ) 2 - 2 5 7 7 - 7 3 2 6 / 2 - 2 5 7 7 - 7 3 2 8 s h a r p e l e c t r o n i c s ( s i n g a p o r e ) p t e . , l t d . 4 3 8 a , a l e x a n d r a r o a d , # 0 5 - 0 1 / 0 2 a l e x a n d r a t e c h n o p a r k , s i n g a p o r e 1 1 9 9 6 7 p h o n e : ( 6 5 ) 2 7 1 - 3 5 6 6 f a x : ( 6 5 ) 2 7 1 - 3 8 5 5 s h a r p e l e c t r o n i c c o m p o n e n t s ( k o r e a ) c o r p o r a t i o n r m 5 0 1 g e o s u n g b / d , 5 4 1 d o h w a - d o n g , m a p o - k u s e o u l 1 2 1 - 7 0 1 , k o r e a p h o n e : ( 8 2 ) 2 - 7 1 1 - 5 8 1 3 ~ 8 f a x : ( 8 2 ) 2 - 7 1 1 - 5 8 1 9 c h i n a h o n g k o n g s h a r p m i c r o e l e c t r o n i c s o f c h i n a ( s h a n g h a i ) c o . , l t d . 2 8 x i n j i n q i a o r o a d k i n g t o w e r 1 6 f p u d o n g s h a n g h a i , 2 0 1 2 0 6 p . r . c h i n a p h o n e : ( 8 6 ) 2 1 - 5 8 5 4 - 7 7 1 0 / 2 1 - 5 8 3 4 - 6 0 5 6 f a x : ( 8 6 ) 2 1 - 5 8 5 4 - 4 3 4 0 / 2 1 - 5 8 3 4 - 6 0 5 7 h e a d o f f i c e : n o . 3 6 0 , b a s h e n r o a d , x i n d e v e l o p m e n t b l d g . 2 2 w a i g a o q i a o f r e e t r a d e z o n e s h a n g h a i 2 0 0 1 3 1 p . r . c h i n a e m a i l : s m c @ c h i n a . g l o b a l . s h a r p . c o . j p s h a r p - r o x y ( h o n g k o n g ) l t d . 3 r d b u s i n e s s d i v i s i o n , 1 7 / f , a d m i r a l t y c e n t r e , t o w e r 1 1 8 h a r c o u r t r o a d , h o n g k o n g p h o n e : ( 8 5 2 ) 2 8 2 2 9 3 1 1 f a x : ( 8 5 2 ) 2 8 6 6 0 7 7 9 w w w . s h a r p . c o m . h k s h e n z h e n r e p r e s e n t a t i v e o f f i c e : r o o m 1 3 b 1 , t o w e r c , e l e c t r o n i c s s c i e n c e & t e c h n o l o g y b u i l d i n g s h e n n a n z h o n g r o a d s h e n z h e n , p . r . c h i n a p h o n e : ( 8 6 ) 7 5 5 - 3 2 7 3 7 3 1 f a x : ( 8 6 ) 7 5 5 - 3 2 7 3 7 3 5

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